The present invention relates to semiconductor devices and manufacturing methods thereof, and more specifically, to a semiconductor device including a semiconductor element for forming a logic circuit, and another semiconductor element for forming an input/output circuit, and a manufacturing method thereof.
A microcomputer is taken as an example of semiconductor devices incorporating a flash memory and a central processing unit (CPU). The microcomputer generally has a number of metal oxide semiconductor (MOS) transistors formed over a semiconductor substrate.
The MOS transistors formed over the semiconductor substrate of the microcomputer include, for example, a core transistor for forming a logic circuit, such as a CPU or a memory, and an I/O transistor for forming an input/output circuit electrically coupled to other semiconductor devices.
For example, the following Patent Documents 1 to 7 disclose semiconductor devices including a plurality of types of transistors formed over the same semiconductor substrate, like the above-mentioned core transistor and I/O transistor.
The core transistor and the I/O transistor are formed over the same semiconductor substrate. However, both transistors differ from each other in power required to drive each of the transistors. In some cases, a voltage of 7 V or more is applied to between a source and a drain, for example, even in the I/O transistor for a 5-V system during burn-in.
In this case, a leak current is more likely to be generated between a support substrate and a silicide region, for example, which is formed by siliciding parts of the source region or drain region by heat treatment. This is because a depletion layer is likely to come into contact with the silicide region of the drain region due to a large voltage applied to the drain region.
Each of Patent Documents 1 to 4 discloses a semiconductor device having a structure with a deep source/drain region (LDD region, impurity diffusion layer) of the I/O transistor as compared to the core transistor. The term “deep” means that a distance between one main surface of the semiconductor substrate and the lowermost part of the source/drain region is long. This arrangement can increase the distance between the silicide region formed in the vicinity of the surface of the source/drain region and a depletion layer upon applying a drain voltage to the I/O transistor, which can suppress the generation of the leak current between the silicide region and the depletion layer.
The technique disclosed in Patent Document 5 involves making a difference in concentration of impurities of a source/drain region (impurity layer) between a core transistor and an I/O transistor, taking into consideration the difference in performance between the core transistor (MOSFET of a logic unit) and the I/O transistor.
Patent Documents 6 and 7 disclose a semiconductor device in which a source/drain region (junction region or the like) of a MOS transistor having a high dielectric breakdown voltage or high breakdown-voltage characteristics is formed more deeply than a source/drain region of a MOS transistor having a low dielectric breakdown voltage or low breakdown-voltage characteristics.